1. Field of the Invention
The present invention relates to nonvolatile memory devices, and more particularly to an improved nonvolatile memory based on floating gate transistors with fast programming.
2. Description of Related Art
Flash memory is a class of nonvolatile memory integrated circuits, based on floating gate transistors. The memory state of a floating gate cell is determined by the concentration of charge trapped in the floating gate. The operation of flash memory is largely dependent on the techniques used for injecting or removing charge from the floating gate.
Low power consumption, adaptability to low voltage operation as well as fast write and read constitute the desirable features for high density flash memory to be used as mass storage media in portable systems.
Much effort has been devoted to developing high density and high performance flash memory. However, there still remain some important aspects to be improved. Two of them are low voltage operation and high program/erase PGM/ERS cycling endurance. Flash memories generally use Fowler-Norcheim (FN) tunneling to inject and emit electrons through tunnel oxide. This means that a high electric field is required for flash memories to achieve high PGM/ERS speeds, and high voltages are needed at least inside the chip. Both high field and high voltage requirements go against low voltage operation and high PGM/ERS cycling endurance.
There are drawbacks associated with all of the various prior art program PGM operation schemes used to inject electrons into the floating gate. Channel Hot Electron Injection (CHEI) requires high current, high power, and causes a hot hole injection (HHI) issue for over-erased cells. Drain Avalanche Hot Carrier (DAHC) is low speed, and suffers a HHI induced reliability issue. Fowler-Nordheim (FN) tunneling suffers a speed/reliability trade-off. High speed leads to severe stress and reliability degradation due to the high fields. Channel FN tunneling suffers the disadvantage that substrate HHI cannot be avoided under increasing FN current. Edge FN tunneling suffers band-to-band tunneling BBT induced HHI which leads to critical reliability issues.
Accordingly, it is desirable to provide a flash memory cell design and operating technique which increases the speed and efficiency of programming of a floating gate memory array, in order to improve the overall performance of the device. Furthermore, it is desirable that the flash memory operating technique be suitable for low supply voltages.
The present invention provides a new flash memory cell structure and operational bias approach for allowing programming operations significantly faster and more efficient than prior approaches, based on the use of band-to-band tunneling induced hot electron injection BBTHEI in cells to be programmed, and in one embodiment on the use of triple-well floating gate memory structures.
Thus, the invention can be characterized as a method for programming floating gate memory cells, in which the cells are formed in a channel well within an isolation well in a semiconductor substrate. For example, in a p-type semiconductor substrate, a deep n-type isolation well is formed. Within the isolation well, a p-type channel well is formed. The floating gate memory cells are formed within the channel well such that the channel areas of the cells reside in the channel well. The invention can also be applied in other semiconductor bodies which are capable of receiving a bias potential.
The method comprises inducing band-to-band tunneling current from the semiconductor body to one of the source and drain near the channel, and applying a positive bias voltage to the control gate to induce hot electron injection into the floating gate. The other of the source and drain terminals is floated, that is disconnected so that current does not flow through that terminal. The band-to-band tunneling current is induced by applying a reference potential to one of the source and drain sufficient relative to the negative bias voltage on the semiconductor body, to establish conditions for the band-to-band tunneling current. For example, a reference potential of approximately 0 volts is applied to the drain, a negative bias of about xe2x88x924 volts to xe2x88x928 volts is applied to the semiconductor body, and a positive voltage is applied to the control gate which falls in a range of about +6 volts to about +10 volts.
In a preferred example, the band-to-band tunneling current through the one of the source and drain which receives the reference potential falls in a range of about 1 to 10 nanoAmperes during the step of inducing band-to-band tunneling current, and the hot electron injection current induced is about 0.5 to 1% of the band-to-band tunneling current. The positive bias voltage applied to the control gate is ramped during an interval of about 5 to 100 microseconds from an initial level to final level. For one example, the control gate voltage is ramped from about 6.5 volts to about 10 volts, over a 10 microsecond interval.
The floating gate transistor according to the present invention comprises a semiconductor body having a first concentration of a first type of dopant, such as a channel well discussed above. A source is formed in the semiconductor body having a first concentration of a second type of dopant, and a drain is formed having a second concentration of the second type of dopant (which may be the same as, or different than, the source doping). A channel in the semiconductor body between the source and drain includes a concentration of the first type of dopant in a range of about 1xc3x971018/cm3 or higher near a surface of the channel. Resources are included with the memory device to induce band-to-band tunneling current from the semiconductor body to one of the source and drain near the channel, and to apply a bias voltage to the control gate to induce hot electron injection into the floating gate as discussed above.
The increased concentration of dopant near the surface of the channel is utilized to enhance the band-to-band tunneling effect. Under the conditions described above, significant band-to-band tunneling current is found to occur when the doping concentration reaches a level on the order of 1xc3x971018 to 1xc3x971019/cm3. Also, for MOS devices like floating gate transistors, where the gate electrode is located above the channel junction at one of the source and drain, band-to-band tunneling current is strongly effected by gate bias.
It is found that band-to-band tunneling current is enhanced by applying a shallow cell implant dose in a channel to enhance the doping concentration near the surface of the channel. Thus, according to one implementation of the present invention, the semiconductor body has a concentration of the first type of dopant that falls in a range of 1xc3x971018/cm3 or higher within about 0.2 microns of the surface. This increased concentration of the first type of dopant is established by a shallow implant of dopants having concentration on the order of 1013/cm2 at an energy between about 70 keV (kilo-electron Volts) and 40 keV, and about 50 keV in one example, in combination with a deeper implant of dopants having a concentration on the order of 1013/cm2 at an energy of between about 100 keV and 150 keV, and about 125 keV in one example.
Thus, the present invention also provides a method for manufacturing a floating gate memory device adapted for band-to-band tunneling induced hot electron injection. The method comprises:
forming a semiconductor body having a first dopant type on and isolated from a semiconductor substrate;
implanting a second dopant type in source and drain regions in the semiconductor body;
implanting the first dopant type in the semiconductor body in a channel region between the source and drain regions so that concentration of the first type of dopants near a surface to the channel region is sufficient to enhance band-to-band tunneling current between the semiconductor body and one of the source and drain regions; and
forming a tunnel dielectric over the channel region and a junction between one of the source and drain regions, a floating gate over the tunnel dielectric, a second dielectric over the floating gate, and a control gate over the second dielectric.
The semiconductor substrate comprises a doped semiconductor material of a first conductivity type, and the step of forming a semiconductor body in one preferred implementation comprises implanting a dopant of the second type relatively deeply to form a deep well of a second conductivity type in the substrate, and implanting a dopant of the first type to form a well of the first conductivity type in the deep well.
The step of implanting the first type of dopant in the semiconductor body within the channel region comprises implanting dopants of the first conductivity type with the concentration on the order of 1013/cm2 at an energy between about 70 keV and 40 keV in the channel, and implanting dopants of the first conductivity type having a concentration on the order of 1013/cm2 at an energy between about 100 keV and 150 keV.
Accordingly, a novel floating gate memory programming scheme has been provided which enables very low current and low power programming of the device. Programming current of less than 1 microAmp per byte can be realized utilizing the techniques of the present invention. In addition, a low gate bias induces less oxide stress during programming. With a gate bias of less than 10 volts, fast programming of about 10 to 15 microseconds per byte is achievable. Furthermore, there is a very high hot electron injection efficiency achieved. The gate current to drain current ratio of about 1 to 100 is achievable.
Other aspects and advantages of the present invention can be seen upon review of the figures, the detailed description and the claims which follow.